20-Mar-06
Synopsys' Verification IP Library For Systemverilog
Synopsys, Inc. has announced that its VCS Verification Library, containing DesignWare verification intellectual property (VIP), is first to support testbenches created using IEEE Std 1800-2005 SystemVerilog and the coverage-driven methodology defined in the Verification Methodology Manual (VMM) for SystemVerilog, published by Springer Science+Business Media. more...

20-Mar-06
Synopsys Delivers First Complete SystemVerilog Design And Verification Flow
Synopsys, Inc. has announced that it now supports the SystemVerilog language throughout its suite of design and verification products. more...